NEC's implementation of this methodology also incorporates the timing-driven feature of the layout tool. In this approach, the design constraints are forward annotated to the place-and-route tool so that it could meet the required timing characteristics without going through tedious timing fix/ECO loops. The optimization capability inside the timing-driven place and route will do the gate re-sizing, repeater insertion, and the buffer/inverter, insertion/deletion needed to meet the required timing specs for the block level, as well as the chip level. You have to start at the top (level)

The fraction of a design that is actually new continues to diminish over the years as a good chunk of designs today consist of pre-characterized blocks. The foremost task in the top-level design phase is to partition the design into a physical hierarchy. This partitioning is done with the connectivity and timing requirements of the complete chip in mind. At the top level, only the I/O blocks and hard macros (such as memories and the partitioned blocks) are present. Flip-flops at the top-level aren't recommended, while hard macros such as memories can reside in the top level or block level. The physical partitioning of the design will make it easier to guarantee better inter-block - as well as intra-block - timing. For example, if particular portions of the design need to work at higher frequencies compared to the rest of the design, grouping them in one physical block will reduce the wire lengths during final route. Register banks are normally added to the physical hierarchy blocks to guarantee the timing (see Figure 2).

Once the top-level partition is completed, the design is then floorplanned. During the floorplan stage the pins are assigned, top level I/O buffers and hard macros such as CPU blocks, memory (RAM/ROM) blocks, and PLLs are placed. The location, size, and shape of each physical hierarchy are determined for the most efficient routability. The location of the pins on the physical macros is identified with routability in mind, a task the floorplan tools perform automatically. Now the BIST, JTAG, scan structures, and macro-test bus structures are placed at the top level to take into account the overheads due to these features. The idea is to get as close as possible to the final top-level design.

This physical partitioning also helps in isolating test structures or clock domains better than in the flat design. We could keep the scan chains or clock trees restricted to a particular physical partition for better efficiency.

Top-level route

The second piece of the top-down, hierarchical approach is to create timing constraints from the logic synthesis tool and forward annotate it to the place-and-route engine. The place-and-route engine could then complete the placement and routing based on these constraints. The success of this approach is due to the early estimation of parasitics, forward annotation of design constraints, and bi-directional flow of information from physical design to logic design - each loop progressively reducing the timing divergence. If implemented well, this approach could substantially reduce the uncertainty of the top-level design process.

Partitioning the design into a physical hierarchy is the most important task at the top level of the design flow.
Once the top-level design is completed, the individual blocks at this level (which are physical hierarchies) are then characterized as block library elements. Some of the blocks at this stage are black boxes, as the register transfer level (RTL) descriptions for them don't yet exist. A black box definition for such blocks is developed using the physical hierarchy it represents. The pin attributes, I/O timings, set-up/hold timings, and clock requirements are specified for each block. Input capacitance, slew rate, output capacitance, and output slew rates are also defined. Identifying the critical pins on the block-level design at this point (even though the block level design doesn't exist yet) will enable the designers to place appropriate timing constraints for them.

Subsequently, the top-level design layout is completed, including power routing, placement, clock balancing, placement optimization, final routing, and max-load fixing. Repeaters are inserted wherever required. Even though clock balancing is performed at the top level, it isn't possible to estimate the insertion delays and skew at this point, because the clock-tree synthesis for the lower-level blocks hasn't been completed. Nevertheless, the root clock-buffer placement and clock-line wiring is finished at this stage. While doing placement at the top level, caution must be taken not to place instances overlapping with the physical partitions. The overlap in placement will make it difficult to move a particular physical partition within the top-level layout. Alternatively, however, this restriction will increase the congestion and decrease the top-level routability. After top-level routing, congestion analysis needs to be performed and if the results aren't promising, several alternate floorplans could be attempted.

Now, design checks for the top level are performed. Since some of the block-level designs don't exist at this time, only the block boundaries are checked. Additionally, clock-tree checks, connectivity checks, shape checks, and antenna checks are done. Repairs are performed if problems are identified. We need to wait for the full chip integration - including the physical partitions - for a complete design check and analysis, however.

Once the layout is completed, parasitic extraction and delay calculations are performed. The delays are calculated for all variations of signal integrity as well. Layout verification for connectivity and geometry violations is also performed. Signal integrity checks, as well as checks for electromigration and hot electron, are also performed. Signal integrity repair is attempted using either placement techniques or routing techniques. The delays are calculated one more time for the top level. Once the top-level timing is satisfactory, the individual blocks are characterized for the appropriate I/O timings.

At this point, we have the overall top-level design completed, which will meet both the timing and the signal integrity requirements. A timing and area budget is available for each of the physical partitions. Logic designers can now design these blocks in RTL according to the specifications. One recommendation is to keep these top-level blocks under 500K gates. Thus, for a 10-million gate design, we may need a minimum of 20 blocks. (Typical designs of this size have several instances of pre-defined hard macros though.) A 500K block is still manageable, however, for a flat layout at the block level.

Yet another benefit of the hierarchical approach is that it follows a very similar methodology for the top-level design, as well as the block design. Also, once the design is partitioned into a few manageable blocks, engineers can work concurrently on them, reducing the elapsed time for the completion of the design. EDA tools work much better at these gate counts when compared to gate counts of two to five million gates.

Block-level design

Block-level design includes the following steps: floorplanning, RTL design, synthesis, DFT insertion, and timing-driven layout including clock-tree synthesis.

For better timing assurance, it's recommended that a register bank be added at the interfaces. During the clock-tree synthesis process, clock buffers are added to the block-level netlist. This buffer is connected directly to the top-level clock buffer. Gated clock-tree expansion could be done at this stage as well. Logic synthesis is performed based on the block-level constraints extracted at the top level. Since the gate count isn't known at this time, an automatic wire-load selection is assumed. Setup times need to be checked in pre-layout stage using the MAX library. Hold check will be performed during timing driven layout or after the layout stage using MIN library.

After synthesis, scan insertion is performed. Once this is finished, delay estimation of the block netlist is initiated. Since the input slew rate and output loading aren't known exactly for each block, there can be differences in the timing characteristics of the block before and after block design. The extent of the changes required at the top level depends upon the divergence of the delay results. Once the SDF file is generated, timing analysis, clock-insertion delay, and clock-skew values can be estimated. Gate-level verification is also performed at this stage. Any verification of pre-scan, post-scan or pre-CTS/post-CTS could be performed using a formal verification tool.

The block design is checked for connectivity errors, clock-tree connections, electromigration, and hot electron. Scan-check connections are also performed. Now, the block-level layout is performed including placement, power routing, placement optimization, routing, and fan-out fixes. Once these tasks are complete, RC extraction starts at the block level. Before the layout is verified, delay calculation is performed, including an accounting for the added effects of signal integrity variations. Succeeding the delay calculation step, electromigration and antenna checks for the block level are soon initiated. Any issues identified at this stage are repaired using placement optimization or using re-routing.

Now timing analysis is performed at the macro level to meet the block-timing budget. Once the individual blocks are completed, the block-level models are regenerated and a top-level timing analysis can be completed. With the timing analysis report, the block libraries are recharacterized (see Figure 3).