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P2020AMC AdvancedMC™ Reference Design
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The P2020AMC is a high density single width, full height Advanced Mezzanine Card based on P2020 communication processor. The P2020 is the next generation multi-core integrated communications processor using 45nm SOI process technology with two e500 cores running up to 1.2 GHz, Security Engine, a memory controller supporting DDR2/3 memory devices, 3 x Gigabit Ethernet interfaces (eTSECs), x4 SERDES block (shared between PCIE/SRIO) USB 2.0, enhanced SDHC (eSDHC) card controller, SPI and an enhanced 32-bit local bus. The P2020AMC has 1GB of DDR2 SOCDIMM Memory and 64MB NOR flash sits on eLBC. For data plane applications, high throughput 3.125GHz x4 RapidIO links connect the P2020 with AMC backplane via IDT’s high bandwidth 10 Port (x4) CPS10Q SRIO Switch. |
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Data/Control plane applications are handled by the 1G Ethernet interfaces. Two 1000 Base-X Gigabit interfaces connect the backplane to the P2020 via Ethernet Switch. The P2020 has three Gigabit RGMII interfaces connected to the backplane via the Ethernet Switch. Two additional Gigabit Ethernet interfaces are provided at the front panel for test and control. Board control and hot swapping are provided by the Pigeon Point based Module Management Controller (MMC)
To aid future development the AMC has been designed around a mezzanine concept. The Mezzanine will provide system building block to enable future AMC prototyping systems to be quickly realized. |
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P2020AMC Hardware Specification
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P2020 Processor
- Two high-performance 32-bit Book E-enhanced cores that implement the Power Architecture™ technology
- 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection.
- Signal-processing engine (SPE) APU. Provides an extensive instruction set for vector (64-bit) integer and fractional operations.
- 512-Kbyte L2 cache/SRAM with ECC
- e500 coherency module (ECM) manages core and intra-system transactions
- Integrated security engine (SEC) optimized to process all the algorithms associated with IPSec, IKE, SSL/TLS, SRTP, IEEE Std 802.16e™, and 3GPP
- 64-bit DDR2/DDR3 SDRAM memory controller with ECC support
- Two four-channel DMA controllers
- High-Speed USB controller (USB 2.0)
- Two I2C controllers, DUART, timers
- Programmable interrupt controller (PIC) compliant with OpenPIC standard
- Enhanced local bus controller (eLBC)
- Enhanced Serial peripheral interface(eSPI)
- Enhanced secure digital host controller (SD/MMC)
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Board IO
AMC Connector
- 2x Gigabit Ethernet Interfaces (Port 0 &1)
- 3.125GHz (x4) Serial RapidIO ports [4:7]
- 3.125GHz (x4) Serial RapidIO ports [8:11]
- 3.125GHz (x4) Serial RapidIO ports [12:15]
- 3.125GHz (x4) Serial RapidIO ports [17:20]
Front Panel
- 2x Gigabit Ethernet Interfaces (RJ45)
- Mini-USB Type B v2.0 USB interface
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Headers and Debug
- P2020 COP Header
- Expansion Connector giving access to
- FPGA JTAG
- MMC JTAG
- MMC UART
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Module Management Controller
- Hot swapping
- FRU storage
- Status LEDs
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Application Areas
- Media Gateway
- RNC
- P2020 Refernce platform in AMC
form factor
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Single Width Full height AMC form factor
P2020 QorlQ™ Communication processor
- Dual high-performance power Architecture e500 cores
- Three 10/100/1000 Mbps enhanced three-speed Ethernet controllers (eTSECs)
- 64Mbytes NOR 16-bit Flash Memory
- 1Gbytes DDR2 Memory in SOCDIMM
- SD/MMC Connector for External Memory Card
Connectivity
- Four 3.125Gbps SRIO x4 interfaces from backplane to P2020 via IDT CPS10Q SRIO Switch
- Either SRIO x4 (3.125Gbps, 2.5Gbps, 1.25Gbps) or PCIE x1 from P2020 is routed to backplane via IDT CPS10Q SRIO Switch
- Two 1000 Base-X Gigabit Ethernet interfaces from backplane to P2020 via Ethernet Switch
- Three RGMII Interfaces from P2020 to Ethernet Switch
- Two front Panel Ethernet Interfaces
Module Management Controller
- Hot swapping
- Board Control
Target Applications
- System component for Media Gateway, RNC and Base band systems
- P2020 design reference and enablement platform for customers and third parties.
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