To achieve high data rate, 8 rows of Flash device arrays are interfaced to the FPGA and FPGA have 8 Flash DMA engines to access the flash arrays and to transfer data between the flash devices and cache.

Flash media physical layout and media architecture

Since many of the terms like block, page etc. are used with different meaning in different context, the following terminology is proposed to be use in FPGA flash Disk project communications, to avoid ambiguity.

Sector: 512 bytes of contiguous data block referred by host in ATA commands for media access (Read and Write). In both CHS addressing and Logical Block Addressing (LBA) mode, sector size is the same (an LBA corresponds to 512 byte sector). Irrespective of the flash device used, this terminology shall be used for the smallest addressable unit (for read and write commands) on flash Disk. For every LBA, there will be a Physical Block Address (PBA) internal to the flash Disk, which corresponds to 512 bytes (sector) on the flash.

Address Translation Table (ATT): A dynamic table (with a persistent information in flash) maintained by firmware to store LBA to PBA mapping.

Cluster: A set of contiguous sectors usually referred by certain file systems to combine hard Disk sectors to form single unit for read and write. For flash Disk, this is relevant only to Read multiple and write multiple commands, and host will set the number of sectors to be combined for these commands, before issuing corresponding read or write command to Disk.

Page: Data locations in NAND Flash devices are logically arranges as rows and columns, and a page represents column in a device. Programming of flash device is done page by page. (Some devices allow interleaved page programming). Since the page size varies for different flash devices, to avoid confusion, we shall avoid referring to this unit in ATT architecture.

Erase Block (EB): A group of pages form a “block” in a NAND flash. The NAND flash devices are erasable only at “block” level. Since the term “block” is used to represent various levels, a specific term “Erase Block” shall be used to refer this.

Allocation Block (AB): Mapping of Logical Block Address (LBA) to Physical Block address is transparent to the host and is purely an internal organization. Various design options are available for this mapping. One extreme scenario is to have one “Erase Block” mapped to contiguous physical address. In this case size of address translation table will be small, but a change in any one sector in the block will lead to erasing of the block before re-use, which will reduce the life of device. This will also reduce the throughput (since flash-block size in large capacity flash devices are typically 128K bytes and reads of up to 128 K byte will have to be read from a single device). Another extreme scenario is to map every sector to one LBA. In this case the ATT becomes very large and cache management also becomes more complex. This also can lead to inefficient DMA transfer from flash device.

An optimum architecture would be to have a few sectors combined together to form an Allocation Block (with contiguous Physical Block Address), to optimize DMA transfer, device life, ATT size etc. A flexibility to tune the Allocation Block (AB) size from 2KB to 16KB shall be provided in firmware. During detailed design and implementation stages, most optimum size can be identified and finalized accordingly. The cache block size also will depend upon the Allocation Block and is an important parameter is firmware design for ATT and cache management.

To achieve optimum data throughputs, ABs correspond to contiguous LBAs shall be distributed among flash stack rows so that multiple flash buses can be utilized for reading from flash.

Spare AB: To avoid instantaneous erasing of ABs as and when it obsoletes, it will be marked as “dirty” for later erasing. PBA from dirty ABs should not be present in the ATT against any LBA. So dirty ABs should be kept as a spare heap of sectors. Similarly to allocate a new PBA against an over written LBA, a “clean” PBA from a clean AB is required (which was not there in ATT). So there has to be a heap of clean ABs also to be maintained. As the clean heap is consumed, dirty heap builds up. Once in a while, the garbage collection task has to withdraw “dirty ABs” from the heap, clean and add to the clean heap, so that there will not be any resource crunch.

Standby AB: The NAND flash devices have an inherent disadvantage of some cells becoming faulty. This can happen initially as well as on the fly (while programming). The flash devices provide on chip features to detect faulty cells initially as well as during erasing and re-programming cycles. If a cell is detected faulty, the complete “device” block corresponding to that cell will have to be marked faulty. To avoid any data losing due to faulty cells, a certain number of blocks are kept aside as standby AB and consumed as when blocks are detected faulty. When the available standby AB count becomes very low, the Disk becomes less reliable. (a command similar to the SMART shall be introduced for the host to get to know the status of standby AB available, as an indication of Disk reliability)

Logical Disk Size: Out of the 24GB physical size of the flash Disk array, a certain amount of space is to be kept aside for spare AB and stand-by AB (to replace the faulty media blocks). So the logical size visible to the host will be less that the actual physical size of the Disk. As a rule of thumb, 10% of space can be reserved for spare and stand-by ABs. So the logical Disk size could be 20GB. (this shall be finalized during detailed design stage, considering the constraints and advantages).

Cache Block Size (CBS): The cache block size shall be kept as same as the AB size, since the sectors in an AB are always maintained together. For a read command for which the requested data is not found in cache, 8 AB size of data starting from the current LBA, shall be fetched from the flash to cache. For eg. in case of a 4K size AB, if host request for a read from LBA “0x0000”, and if cache search fails (no hit), firmware shall initiate DMA read from 8 ABs corresponding to LBA 0x0000-0007 from flash stack row 1, LBA 0x0008-000F from row 2 and so on till LBA 0x0038-003F from row 8. Since these ABs will be distributed over flash stack rows, simultaneous reads from all 8 rows will be possible to get maximum throughput.

Cache Page Size (CPS): To keep data corresponding to one AB each from each of flash array rows, a logical paging of cache of 8 times CBS shall be maintained.