SDRAM Controller

GDA's SDRAM controller core is a fully synchronous, highly modular, and highly configurable design targeted for a wide range of applications and technologies

The application dependent front end is implemented as separate module with clearly defined interface to the rest of the design. This enables quick customizing of the core for different designs. The application interface to the controller provides a completely de-coupled request and data transfer mechanisms to allow very high data bandwidth.

The interface supports a configurable number of agents, which can vary from 1 to 8. The controller architecture enables pipelining of multiple requests to improve overall memory access bandwidth.

The front-end interface is simple and timing friendly that enables easy integration of the core through on-chip buses or point-to-point connections.

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* -Generally sold with GDA services only

Features
Supports 100 MHz SDRAM interface in ASIC implementations 6-1-1-1 burst read operation in 100 MHz Configurable data width and memory depth Supports multiple memory accessing agents Supports up to 8 banks of memory (CS# lines) Supports 16 Mbit, 64 Mbit and 256Mbit SDRAMs	Configurable buffering on read and write paths De-coupled request and data lines for high data throughput Configurable CAS latency, burst length, number of banks and row/column address widths Multiple arbitration schemes for multi-agent implementations

Features

Supports 100 MHz SDRAM interface in
ASIC implementations

6-1-1-1 burst read operation in 100 MHz

  Configurable data width and memory depth

  Supports multiple memory accessing agents
  Supports up to 8 banks of memory (CS# lines)

  Supports 16 Mbit, 64 Mbit and 256Mbit SDRAMs

  Configurable buffering on read and write paths

  De-coupled request and data lines for high data throughput

  Configurable CAS latency, burst length, number
    of banks and row/column address widths

  Multiple arbitration schemes for multi-agent implementations