GDA's HDLC Controller is a single-channel HDLC controller core. The device contains a full-duplex transceiver with independent transmit and receive sections for bit-level HDLC protocol operations.
The core is designed for easy integration into wide range of applications implemented on most ASIC and FPGA technologies. The interface of this core can be adapted for a wide range of FIFO controllers. To be filled
* -Generally sold with GDA services only
Flag insertion and detection
Abort generation and detection.
Zero bit stuffing and deletion
Automatic insertion of 1 to 255 IDLE Characters