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Interlaken IP Core

Product Brief

The Interlaken is a high speed, narrow, channelized and highly configurable chip-to-chip interface protocol. It offers programmable burst sizes, per-channel backpressure, source-asynchronous nature and scalability. Its high bandwidth range design makes it utilizable for existing network application as well as next generation high speed application. It has low numbers of IOs as compared to SPI4.2 interface which has been used by most of the existing networking applications. Interlaken can be used in a Framer/MAC to NPU or L2/L3 switch Interface, Line Card to Switch Fabric Interface.

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GDA Technologies Inc. is a leading Electronic Design Services (EDS) and Silicon Intellectual Property (SIP) solution provider for the Embedded, Networking, and Consumer Electronics Markets. GDA is focused on designing IC and board level products from concept to implementation. GDA has successfully developed products in areas of high-speed communications, Digital Video, Internet Appliances, and Mobile Solutions.

IP Status

RTL coding for Data width of 64bit, 128 bit done, 256 bit ongoing Functional Verification - ongoing

Product Package

* Highly Configurable RTL code using the VPP option
* Detailed Design/Verification document
* Verification environment
* Test cases
* Coverage Reports
* Synthesis environment/Scripts

Documentation

* User Guide
* Synthesis Guide
Language :Verilog HDL
Synthesis:RTL Compiler
Simulation:NC-Verilog
Technology:Technology Independent RTL



Features

  Support for 256 communications channels

  Self synchronization data scrambler & descrambler.

  64B/67B data encoding, decoding
  Supports both packet mode and segment mode

  Configurable number of lanes from 1 to 20
  Configurable User side data bus width of 64,128 and 256 bits
  Configurable BUSTMAX and BURSTMIN size
  Configurable MetaFrame length

  Support in-band flow control
  Generic SerDes interface with width of 16, 20,
    32 & 40 bits.
  Error Detection and Reporting

Compliance
  Interlaken Protocol Definition -A Joint
    Specification of Cortina Systems and
    Cisco Systems Revision 1.2 October 7, 2008

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