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Gen1 PCI Express- AMBA AHB Bridge

Applications

* PC’s workstations and servers
* Storage
* Networking and communications
* Switches and routers

Benefits

* Verified with leading AXI VIP
* Superior architecture-high performance, low latency and low gate count
* Feature rich, highly flexible, scalable, configurable and timing friendly design
* Ease of integration


PCI Express –AMBA AHB Bridge

The GDA PCI Express*-AMBA AHB Bridge is a highly flexible and configurable IP with the PCI Express interface on one side and an AMBA sub system on the other side. The Bridge has been architectured to interface with a PCI Express controller used as an end-point or root-complex devices. The IP uses high speed multi-channel DMA controllers to match the bandwidth requirements of a PCIe Gen2 solution. The design supports AHB PIO, PCI Express PIO, and Write DMA and read DMA types of transfers.

Superior Architecture

The GDA PCI Express-AMBA AHB Bridge is a simple, configurable and layered architecture which is independent of applications, implementation tools or target technology. The controller architecture is carefully tailored to optimize latency, power consumption, and silicon footprint, making it ideal for cost and performance sensitive applications. The solution provides highly scalable bandwidth through a configurable data path width and clock frequency, thus allowing for a highly optimized solution applicable in a wide range of applications.

Most Thoroughly Verified and Interoperable Design


The GDA PCI Express - AMBA AHB Bridge is an exhaustively verified solution and is fully tested against design specific and protocol compliance checklist. The comprehensive random tests ensure a very high coverage. The IP is verified with leading AHB verification IP’s and the verification environment can be configured to run with all the major simulators. The reusable block level verification environment and the formal verification methodology enhance the quality of verification process and add more confidence to the design verification.

The GDA PCI Express-AMBA AHB Bridge solution leverages years of experience in creating IP for Ethernet, RapidIO and PCI Express technologies. The expertise in creating system validated solutions with RTL, synthesis, Simulation, board and software elements ensures delivery of lower risk, compliant and interoperable solution.

Ease of Integration

The GDA PCI Express- AMBA Bridge design is fully synchronous and adheres to standard synthesis, test insertion and physical design practices. The solution allows licensees to easily migrate among COT, FPGA, Gate array, Structured ASIC and Standard cell technologies. The IP with its flexible user logic interface can be easily integrated into a wide range of applications.

Design Configurability

The design offers enormous hardware and software configurable options allowing the user to choose the optimal solution to meet his requirement. The configuration options include

* PIO, DMA or mixed mode of operation
* Up to 8 Read and Write DMA supported
* Maximum Number of PCI Express capable AHB Slave PIO devices supported (0 - 15)
* PCI Express Receive and Retry buffer size
* VC arbitration scheme
* Maximum DMA transfer size of 1 MB
* Register based or Chain Descriptor based DMA types
* Priority level transaction initiations by different DMA/PIO devices
* Programmable address mapping for PIO transfers
* Programmable PCI Express tags reserved for each DMA/PIO device
* PCI Express or AMBA hosted DMA accesses
* AHB or APB register space accesses
* System clock frequency
* Synchronous/Asynchronous reset

Deliverables

The deliverables include

* Verilog RTL
* Behavioral test bench and test cases
* AMBA AHB, PCI Express and Application BFM
* ASIC Synthesis environment
* Documentation



Features

  Gen1 PCI Express to AMBA AHB Bridge for PCI Express     Base 1.1* (2.5 Gbps)
    specification

  Data path width: 32, 64 and 128-bits

  Interrupt generation to both AMBA and PCI
    Express supported

  Vendor defined messages supported
  Software configurable address mapping between PCI
    Express and AMBA systems

   Exhaustive Control, Status and Debug registers
  CSR registers optional access through APB

    PCI Express Features
   Maximum link width: x16 link
   Max payload size of 4096b

  Up to 8 Virtual Channels supported
  Up to 8 functions supported

  Efficient Receive VC buffer implementation
  Configurable Receive VC buffer size
  PCI Express ordering rules implemented
  INTx, MSI and MSI-X interrupt mechanisms

    AMBA AHB Features
  AMBA AHB 2.0 compliant
  Full and Lite mode operation supported
  AMBA PIO operation with configurable number of AHB
    Slaves supported
  PCIE PIO operation with configurable number of AHB
    Masters supported

  Multi-channel DMA transfers supported
  Register based and descriptor based
    modes of DMA supported

  Optional configurable number of Read
    and write DMAs supported

    Debug and Test Features

    The solution provides comprehensive
    debug and test features such as

  Implementation specific registers for debugging
  Comprehensive error reporting
  Mailbox registers for higher layer
    information exchange

  Performance monitors
  Debug mode for descriptor based DMA
  Interrupt generation for debug mode events

Power Management Features

The design supports mandatory and most
of the optional PCI Express power management
features such as

 L0, L0s, L1, L2 power management states, beacon,     PME and auxiliary power
  Full PCI-PM and ASPM Support for L0s, L1

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