SPI4 Validation Platform (IPEB) is an evaluation platform intended for validating a variety of RTL cores. The IPEB architecture is optimized for high-density and high- performance logic designs. The rich feature set, based on today's high speed networking technology, allows functional testing of various types of Intellectual Property cores by using two Xilinx Virtex II XC2V3000 FPGAs allowing prototyping an ASIC equivalent of approximately two million gates. The board provides for easy configuration of the FPGA through a JTAG connector or through an EEPROM.

The powerful Net +50 ARM processor controls the device/board functions and monitors the test. The board can validate 1G Ethernet cores, 10G Ethernet cores, PCI, and PCI-X cores apart from SPI4 cores. Each Virtex FPGA is provided with one high-speed connector that can interface with a daughter card.

The smart device is used to generate traffic and this traffic is translated to Ethernet traffic using PM3388 device on daughter card. The validation platform supports testing of DUT with variable frame length, variable inter frame gap and allows testing of data and status paths of the SPI4 core by providing pause flow control. There are test points provided to monitor all critical signals.