IPEB is an evaluation platform intended for validating a variety of RTL cores. The IPEB architecture is optimized for high-density and high- performance logic designs. The rich feature set, based on today's high speed networking technology, allows functional testing of various types of Intellectual Property cores by using two Xilinx Virtex II XC2V3000 FPGAs allowing prototyping an ASIC equivalent of approximately two million gates. The board provides for easy configuration of the FPGA through a JTAG connector or through an EEPROM.

The management portion includes a CPU subsystem using Net+50 processor from NetSilicon supported by 1MB Flash Memory and 4 MB SDRAM. There is a serial port and an Ethernet management port available on-board to facilitate debugging. The first FPGA intended for validating networking cores like XGMAC, GMAC, SPI-4 and POSPHY- L3, has two 1-Gigabit Optical interfaces. Typically one is used to generate traffic to the Virtex FPGA and other acts as the output network port. In addition, there is a one 1-Gigabit Optical interface that directly interfaces with the FPGA for testing cores like Gigabit Ethernet MAC. Each Virtex FPGA is provided with one high-speed connector that can interface with a daughter card. One of the high- speed connector provides a SPI-4 interface while the other connector is a general-purpose interface. The other FPGA is connected to 32MB of Flash Memory and SDRAM (SODIMM) and is intended for validating IP Cores like CPU, SDRAM and PCI-X. The board can operate as a standalone hardware module or a PCI/PCI-X add-on card. There is an ATX power input connector to support IPEB-3000 in the standalone mode. In the PCI mode, power is drawn from the PCI connector. The platform is validated with NetSilicon's NetOS® Operating System.