is an FPGA based test board for HyperTransport
core validation. The system can be divided
into two different sections connected
together by a 32bit PCI bus running at
66MHz. The first section is an FPGA with
two HyperTransport interfaces (HT connector
is compliant to HyperTransport Consortium
V.14 document) and one SPI4.2 (System
Packet Interface 4 Phase 2) interface.
The other section is CPU subsection, which
consist of MPC8245 CPU, 128MB MB SDRAM,
one Gigabit Ethernet port, one RS232 port,
256Kb of serial EEPROM, FPGA die temperature
monitor and board temperature monitor
and the Real time clock.
The board is targeted for verifying
the Hyper Transport core with Xilinx
Vertex II series of FPGAs and it supports
Xilinx Virtex II XC2V4000, XC2V6000
and XC2V8000 FPGAs. The board can be
used in many different configurations
to test and validate the Hypertransport
cores. On the basis of topology of HyperTransport
bus standard this can be used in Tunnel
configuration and Cave configuration.
The Hypertransport connector interface
section has two back-to-back Samtec
QSE and QTE connectors to support tunnel
and cave interfaces.