MIPI D-PHY

Silicon Proven
MIPI Compliant

The MIPI PHY (D-PHY) specification defines an interface between the MIPI lanes and MIPI core engine like MIPI DSI or CSI. This interface is defined by MIPI consortium, which defines a series of modules in a MIPI compliant product.

GDA MIPI D_PHY is used in mobile and high –speed serial applications where a MIPI lane is involved. GDA MIPI D_PHY adheres to MIPI D-PHY Specification. The GDA MIPI D-PHY along with GDA MIPI CSI Transmitter or CSI Receiver or DSI Host or DSI Slave provides a complete solution for encoding oe decoding MIPI data.

Design Attributes
• Highly modular design
• Fully synchronous design
• Active low Asynchronous reset

Product Package
• RTL code
• Detailed design document
• Verification environment
• Test cases
• Synthesis environment/scripts

Documentation
• Design Guide
• Synthesis guide

GDA Technologies Inc. is a leading Electronic Design Services (EDS) and Silicon Intellectual Property (SIP) solution provider for the Embedded, Networking, and Consumer Electronics Markets. GDA is focused on designing IC and board level products from concept to implementation. GDA has successfully developed products in areas of high-speed communications, Digital Video, Internet Appliances, and Mobile Solutions.

Features
Compliant with MIPI D-PHY Spec v0.9   Programmable 1, 2 or 4 Data Lane Configuration.   Supports High-Speed and Low-Power modes	Operate in continuous and non-continuous clock modes.   Data Rate: 800 Mbps per lane on silicon (Spec mentions a max of 500 Mbps per lane) in High-Speed mode and 10Mbps in Low-Power mode.

 

Availability : Now
Language : Verilog HDL
Synthesis : Design Compiler, FPGA : Xilinx ISE on Virtex 5
Simulation : Modelsim, Verilog NC