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System Level Modeling
SoC/ASIC & Verification
FPGA/Structured ASIC
Physical Design & DFT
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GDA provides system level modeling support for hardware-software co-simulation, architectural exploration and performance modeling activities preceding ASIC/SoC design phase. This enables our partners to significantly lower the risk of a prolonged ASIC as well as software development cycle.

GDA offers Matlab, OPNET, SystemC, C/C++ modeling for architecture evaluation as well as system and RTL level co-verification.

  Switch Fabric and Ecosystem Model
   
 
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Instruction Set Simulator Model

 

   
   
 
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Testimonials
 

“Based on their extensive IC design and implementation experience we felt GDA Technologies would successfully deliver the services we need on time. In addition to their background in ASIC design, GDA Technologies’ experience in
Structured ASIC and full COT design were considerations in choosing them as a partner.” -

- Terry Hulett

Vice President of Engineering
NetEffect, Austin
October 11, 2004

 
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