System level modeling, Planning and Specification
   IP integration
   Micro-architecture and design specification
   RTL Design and Verification
   Property checking, model checking and assertions
   System and RTL co-simulation
   Synthesis and STA
   Gate level Verification
   Front and Back end Design For Test (DFT ) Services
   Floor Planning, Power planning, Place & Route, and Timing       Closure
   Formal Verification and Equivalency Checking
   Physical verification and tape out.

   Test Strategy and Plan
    Architecting Verification Environment
   Verification IP strategy
   System level and RTL co-simulation
   Test case development
   Regression Automation and Distribution