|
|
|
| |
 |
|
 |
|
Current Openings |
|
|
|
|
|
|
|
|
|
| |
Position in San Jose, CA for Member of Technical Staff (Hardware) with the following skills:
Develop hardware system architecture for embedded controllers and networking, including engineering specification and acceptance criteria; Board design based on different processor chips (Intel, TI, Analog Devices, Atmel), including routing and mechanical guidelines; Board debugging, including use of logic analyzer and digital oscilloscope for diagnosing problems and soldering station to apply required reworks; Low-level programming using C, C++, and Assembly to debug hardware system; Perform system design validation and test; Develop and capture schematic in OrCAD; Perform PCB design, including placement, routing, signal integrity verification; Implement telecommunication protocols using OOD principles.
Also use: Linux, Linux kernel architecture, TI and DspBios.
Require: Bachelor’s degree or equivalent in Computer Sciences/Electric Engineering/Chemical Engineering/Math/Chemistry + 2years experience in duties.
Respond to HR, GDA Technologies, 1010 Rincon Circle, San Jose, CA 95131 |
| |
|
| |
Member of Technical Staff (MTS) ASIC Design:
Perform ASIC & FPGA [Field Programmable Gate Array] design & development (including understanding customer requirements,creating logic design specifications, performing RTL [Register Transfer Logic] language based coding, creating test environment for ASIC chip verification, performing synthesis & creating gate level netlist, and performing timing analysis) using PCI express and HighperTtransport high speed interconnect protocols.
|
| |
Submit resume to GDA Technologies, Inc., San Jose, CA at fax (408) 432-3091 |
| |
|
| |
Member of Technical Staff (MTS) Board Design:
Perform board design, development, & support (including understanding customer requirements, creating engineering specifications, performing schematic capture, overseeing layout design, providing PCB fab & assembly support, performing board bringup & testing, providing customer support).
|
| |
Submit resume to GDA Technologies, Inc., San Jose, CA at fax (408) 432-3091. |
| |
|
| |
Job#007a
Member of Technical Staff, IC Physical Designs:
Location: India, Chennai.
ASIC design & development (including understanding customer requirements)
ASIC backend physical design; ASIC backend physical verification & DFM (design for manufacturability)
ASIC full chip assembly
Writing automating scripts.
Bachelor's or equiv foreign degree in EE or Comp Eng
Requires setup & execution of complete ASIC physical design flow using
- Synopsys,
- Cadence, &
- Magma tools
Full chip assembly & tape-out to foundry;
PERL, TCL, & TK scripting languages. |
| |
 |
| |
Job#008a
Senior Member of Technical Staff, IC Physical Designs: :Location: India, Chennai.
Thorough hands-on Knowledge of Physical design activities such as
- Floor planning
- Placement
- Routing
- Clock tree synthesis
- Static timing analysis
- Signal integrity analysis
- Power verification
- Formal Verification
- Timing optimization
- Physical verification
Experience in
- SoC Encounter Flow
- Timing Closure
- STA
- Signal Integrity IR Drop Analysis
- Design For Manufacturing
- Physical Verification
- Physical Synthesis
Knowledge in Magma Blast Fusion, Astro, Hercules a plus
Must possess good communication skills
Must have excellent project execution skills
Must be highly motivated and team player
Experience with TCL and Perl a plus
Experience of working with Multiple ASIC vendors will be an asset. |
| |
 |
| |
IT Manager:
Manage 3-5 Systems Engineers who install & configure servers with different operating systems, who support the servers, PCs, & work stations, and who install patches for the designing tools;
Use Solaris, Redhat, & Windows OS.
|
| |
 |
| |
Principle Design Engineer:
RTL (register transfer logic) design & implemention using frontend and backend CAD tools;
Synthesis & DFT (design for testability) using Synopsys & Mentor Graphics tools; post silicon verification;
Static timing analysis using Prime Time tool;
Place & route using Cadence First Encounter & Sierra Pinnacle tools;
Use CAD & deep submicron methodologies.
|
| |
 |
| |
Engineering Manager:
Supervise 3-5 System Software or ASIC Engineers who design, develop, test, & implement embedded tools & applications;
Perform requirement analysis, project planning, status reporting, & tracking;
Provide pre-sale support and write project proposals for customers.
|
| |
 |
| |
Chip Verification Lead:
Perform chip verification (including development of methodologies, test plans, compliance test suite, test bench creation, & test cases) using System Verilog, SystemC, C++, & VERA;
Develop scripts;
Develop test bench components (like BFM, transactors, assertions, coverage, protocol monitors, & checkers);
Manage regression;
Perform board validation;
Manage code releases. |
| |
 |
| |
Sales & marketing associate in India |
| |
Location: India (Chennai/Bangalore)
Position Overview:
Primary role is to identify new sales leads for the US region and renew business discussions with past customers and handoff to sales account managers.
Web research for new leads
Update Sales database, entering and organizing.....
|
| |
Learn More  |
| |
 |
| |
 |
| |
Sales Manager position in India |
| |
Location: India
Positions open in Bangalore and Chennai.
Sales Territory : India , Europe, Asia Pacific (excluding Japan )
Position Overview:
Sales candidates will be involved with selling Electronic Design Services in any and all of the following areas: IC Development (ASIC, FPGA), Hardware (board design, pcb design), and Embedded Software (Linux, device drivers…).
Selling and licensing of GDA's Silicon Intellectual Property (SIP) portfolio.... |
| |
Learn More  |
| |
 |
| |
 |
| |
Member of Technical Staff, ASIC Design: Job# 007
ASIC design & development (including understanding customer requirements)
ASIC backend physical design; ASIC backend physical verification & DFM (design for manufacturability)
ASIC fullchip assembly
Writing automating scripts.
Bachelor's or equiv foreign degree in EE or Comp Eng
Requires setup & execution of complete ASIC physical design flow using
- Synopsys,
- Cadence, &
- Magma tools
Fullchip assembly & tapeout to foundry;
PERL, TCL, & TK scripting languages.
|
| |
Submit resume to GDA Technologies, Inc., San Jose, CA
at fax (408) 432-3091, attn: Job 007. |
| |
|
| |
 |
| |
Member of Technical Staff, ASIC Design: Job # 006
Perform ASIC & FPGA design & development (including understanding customer requirements, creating logic design specifications, performing RTL language based coding,
creating test environment for ASIC chip verificationperforming synthesis & creating gate level netlist, and performing timing analysis).
Master's or equiv foreign degree in Electronics Eng or Comp Eng.
Will accept a Bachelor's or equiv foreign degree in Electronics Eng or Electrical Eng with 5 yrs of related, post-Bachelor's, progressive experience in job offered or as ASIC Design
Engineer, in lieu of Master's.
Requires Verilog language;
- ASIC design & synthesis;
- Place & route tools;
- Llayout edit tool (like Virtuoso);
- Physical verification tools (like Dracula & Calibre).
|
| |
Submit resume to GDA
Technologies, Inc., San Jose, CA at fax (408) 432-3091, attn: Job 006. |
| |
|
| |
 |
| |
Hardware Engineering Manager:
Supervise 1-3 Hardware Engineers who
- Perform board design
- Development
- & Support (including understanding customer requirements, creating engineering specifications, performing schematic capture, overseeing layout design, providing PCB fab &
assembly support, performing board bringup & testing, & providing customer support).
Master's or equiv foreign degree in Electronics & Communication Engineering or EE.
Will accept a Bachelor's or equiv foreign degree in Electronics &
Communication Engineering or EE with 5 yrs of related, post- Bachelor's,
progressive exp in job offered or as Design Engineer, in lieu of Master's.
Requires high-speed embedded system design in
- computing,
- networking,
- semiconductors & industrial automation;
- supervision of hardware or design
engineers;
- PCB board design;
- failure analysis.
|
| |
Submit resume to GDA
Technologies, Inc., San Jose, CA at
fax (408) 432-3091. |
| |
|
| |
 |
| |
Sr. Technical Trainer (ASIC Design Service Group)
Provide ASIC development training to members of ASIC technical staff, technical sales team, program managers, and company customers.
Design and develop training materials using ASIC synthesis tools such as
- Synplicity’s Amplify ASIC,
- Synopsys’ Physical Compiler and PrimeTime,
- Magmas’ Blast Fusion;
Provide training using EDA tools such as
- NC-Verilog, VCS,
- Modelsim, Debussy,
- Formality and Conformal-LEC,
- Organize and develop training procedure annuals.
Monitor evaluate and record training activities.
Educational Requirements:
Master’s* degree or equivalent in Electrical Engineering + 6 months of experience in job offered or related field (*in lieu of a Master’s degree, Employer will accept a Bachelor of Science or equivalent in Electrical Engineering or related field plus 5 years of progressive experience or suitable combination of education training or experience). |
| |
Please contact : Mahalakshmi Krishan, GDA Technologies, Inc. 1010 Rincon Circle, San Jose, CA 95131 |
| |
|
| |
 |
| |
Member of Technical Staff, IC Solutions
Experience in
- SoC Encounter Flow
- Timing Closure
- STA
- Signal Integrity
IR Drop Analysis
- Design For Manufacturing
- Physical Verification
- Physical Synthesis
Knowledge in Magma Blast Fusion, Astro, Hercules a plus
Must possess good communication skills
Must have excellent project execution skills
Must be highly motivated and team player
Experience with TCL and Perl a plus
Thorough hands-on Knowledge of Physical design activities such as
- Floor planning
- Placement
- Routing
- Clock tree synthesis
- Static timing analysis
- Signal integrity analysis
- Power verification
- Formal Verification
- Timing optimization
- Physical verification
Experience of working with Multiple ASIC vendors will be an asset. |
| |
Please email resumes to: hr@gdatech.com |
| |
|
| |
|
|
|
|
|
|
|
|
|