Home | Careers | Contact Us  
Company System/Board Services IC Solutions Reference Designs IP Portfolio Customers-Partners News Resources
 
Get a Quote
Send us an email
View all IPs
 
 
Testimonials
 

 
  Learn More  
 
  Quick Links
Silicon IP
IP Enabled Services
Engagement Models
Support & Training
Deliverables
Other IPs
 

Security IP Core - Triple DES

Low-Area
Serial Implementation
NIST Compliant DES Core

Triple DES (TDES) is a secure variant of Data Encryption Standard (DES). It was first proposed by IBM in 1978 and specified in ANSI X9.52 standard. TDES is a symmetric-key and block cipher that accepts 64-bit input data. The keys are 64-bits in size. There are multiple keying options available as suggested by the standard:

1. Three independent keys: K1, K2, K3
2. Two independent keys: K1=K3, K2
3. Three similar keys: K1=K2=K3


The core performs Encryption and Decryption in Encryption-Decryption-Encryption (EDE) and DED format respectively. For a serial version of T-DES, a single encryption/decryption operation has fixed latency of 48 cycles. For a pipelined version, there is 48 cycle initial latency and result is generated every 16 cycles thereafter. The core also supports CBC, CTR, OFB, and CFB modes of operation.

The higher key size in TDES makes it less vulnerable to brute force attacks and has wide applications in the areas of banking, video broadcasting, surveillance and other secure forms of communication.

Specifications
Implementation Results for V4

* 764 slices
* Performance: 110.7MHz
* No Block RAMs
* 301 IOBs
* 48 cycles (E/D), 1.33 bits/cycle

Design Attributes

* Highly modular design
* Fully synchronous, technology-independent design
* Single clock

Product Package

* RTL code
* Detailed design document
* Verification environment
* Test cases
* Synthesis environment/scripts

Documentation

* Design Guide
* Synthesis Guide

Availability :Q1 FY08L
Language:Verilog HDL
Synthesis:Synplify Pro, Xilinx ISE, DC
Simulation : Verilog-NC, VCS, MTI
Technology :0.18u ASIC or better, FPGA

GDA Technologies Inc. is a leading Electronic Design Services (EDS) and Silicon Intellectual Property (SIP) solution provider for the Embedded, Networking, and Consumer Electronics Markets. GDA is focused on designing IC and board level products from concept to implementation. GDA has successfully developed products in areas of high-speed communications, Digital Video, Internet Appliances, and Mobile Solutions.



Features

  Compliant with FIPS 46-3 and ANSI X9.52 standard

  Supports encryption and decryption

  Supports multiple keying options
  Supports ECB mode of operation

  No dead cycles for key loading and encryption
    decryption change
  Fully functional and synthesizable Verilog
     HDL core available
  Verified with a C model using Verilog PLI
    Test environment