Low Area
FIPS 180-2 Compliant
NSA Suite B Algorithm
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Secure Hash Algorithm (SHA) was standardized by NIST in 2002 and published in FIPS 180-2. It is listed among the NSA Suite B list of secure algorithms. SHA-256 is a message digest algorithm that operates on 512-bit block using a compression function and generates a 256-bit hash output. The upper limit check of input text (2 64 – 1) is not part of the logic.
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Pin Diagram
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Timing Waveform for SHA-256 first message block
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Timing Waveform for SHA-256 last message block
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SHA-256 IP core is divided into main module and core module. The main module performs padding and counting of messages. The core module performs the compression operation. For a single 512-bit block it takes 67 cycles to generate a 256-bit hash output. It accepts hexadecimal input data of 32-bit width. The IP Core has been cross-verified with a C-model using a Verilog PLI test environment.
SHA-256 is a commonly used hash algorithm, which finds its applications in data storage, pseudorandom number generation, signature/verification during data transfer, etc. |
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| Specifications |
Implementation Results for V4
- 892 slices, Performance: 90.5MHz
- No Block RAMs, 297 IOBs
- 67 clock cycles for a 512-bit block
- Throughput: 691.58 Mbps
Design Attributes
- Modular design
- Fully synchronous design
- Single clock
Product Package
- RTL code
- Detailed design document
- Verification environment
- Test cases
- Synthesis environment/scripts
Documentation
- Design Guide
- Synthesis guide
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Availability : Q1 FY08
Language : Verilog HDL
Synthesis : Synplify Pro, Xilinx ISE, DC
Simulation : Verilog-NC, VCS, MTI
Technology : 0.18u ASIC or better, FPGA |
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| GDA Technologies Inc. is a leading Electronic Design Services (EDS) and Silicon Intellectual Property (SIP) solution provider for the Embedded, Networking, and Consumer Electronics Markets. GDA is focused on designing IC and board level products from concept to implementation. GDA has successfully developed products in areas of high-speed communications, Digital Video, Internet Appliances, and Mobile Solutions. |
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FEATURES |
- Compliant with FIPS 180-2 standard
- Accepts 32-bit input text in hexadecimal format
- Generates 256-bit hash output
- Fully verified using NIST test vectors
- Fully functional and synthesizable Verilog HDL core available
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