RFC 1321 Compliant
Modular design
Technology independent
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MD5 was developed by Ronald Rivest of MIT in 1991 and published as an internet standard RFC 1321 in Internet Engineering Task Force (IETF). MD5 is a message digest algorithm that operates on 512-bit block using a compression function and generates a 128-bit hash output. The upper limit check of input text (2 64 – 1) is not part of the logic. |
Pin Diagram
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Timing Waveform for MD5 first message block
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Timing Waveform for MD5 last message block
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MD5 IP core is divided into main module and core module. The main module performs padding and counting of messages. The core module performs the compression operation. For a single 512-bit block it takes 67 cycles to generate a 128-bit hash output. It accepts hexadecimal input data of 32-bit width. The IP Core has been cross-verified with a C-model using a Verilog PLI test environment.
MD5 is a commonly used hash algorithm, which finds its applications in data storage, pseudorandom number generation, signature/verification during data transfer, etc.
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| Specifications |
Implementation Results for V4
- 1508 slices, Performance: 75 MHz
- No Block RAMs, 169 IOBs
- 67 clock cycles for a 512-bit block,
- Throughput: 573.13 Mbps
Design Attributes
- Modular design
- Fully synchronous design
- Single clock
Product Package
- RTL code
- Detailed design document
- Verification environment
- Test cases
- Synthesis environment/scripts
Documentation
- Design Guide
- Synthesis guide
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Availability : Q1 FY08
Language : Verilog HDL
Synthesis : Xilinx ISE, DC
Simulation : Verilog-NC, VCS, MTI
Technology : 0.18u ASIC or better, FPGA |
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| GDA Technologies Inc. is a leading Electronic Design Services (EDS) and Silicon Intellectual Property (SIP) solution provider for the Embedded, Networking, and Consumer Electronics Markets. GDA is focused on designing IC and board level products from concept to implementation. GDA has successfully developed products in areas of high-speed communications, Digital Video, Internet Appliances, and Mobile Solutions. |
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FEATURES |
- Accepts 32-bit input text in hexadecimal format
- Generates 128-bit hash output
- Verified with a C-model using Verilog PLI Test Environment
- Fully functional and synthesizable Verilog HDL core available
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