Configurable Viterbi Decoder/Encoder is a highly configurable architecture for design reuse. Viterbi decoders are widely used in digital communication systems. Depending on the application, CVD can be configured for specific code parameter requirements.
The design employs Add-Compare-Select (ACS) parallelism and pipelining for performance scalability. The trellis and path metric memory addressing is configured accordingly.
The design provides a real-time or bus input/output interface and a Bit Error Rate (BER) monitor. It also supports punctured symbol data input and synchronization. The design is modular, fully synthesizable and can be configured for the speed and area requirements of the application.