CUSB2DEV is a highly configurable USB
2.0 device Controller core. It can
be easily integrated into ASIC as well as FPGA.
The PBUS & SBUS interface allows the core
to be integrated with any other applications,
which requires USB 2.0 interface.
The controller architecture is carefully tailored
for high throughput, low latency, better reliability,
and low power consumption. The controller's
simple, configurable and layered architecture
is independent of application logic, PHY designs,
implementation tools and, most importantly,
the target technology. The hardware configurable
feature such as number of endpoints allow the
core to be used by multiple applications which
can share the USB bus bandwidth among them through
SBUS interface.
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| * - Generally sold with GDA services only |
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Features |
- Supports High/Full/Low
speed devices
- UTMI 8-bit Unidirectional
compliant
- Optional UTMI 16-bit
bi-directional support
- Optional USB 1.1 PHY
support
- Optional DMA controller,
configurable built-in FIFO for each
end point.
- Direct FIFO interface
in absence of DMA
- Hardware configurable
number of endpoint
- Software configurable
endpoint number, type and packet size
- Supports 4 configurations,
4 interfaces, 4 alternative Interfaces
and 16 endpoints
- Suspend, Resume and
Wakeup logic is provided
- Optional Endpoint
Zero block: supports all standard requests
except set Descriptor command, and sync
frame command.
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