GDA's PCI controller core is a technology independent, fully synchronous, highly efficient, 32/64-bit implementation compliant to PCI Local bus specification, rev 2.2
The controller is designed to function at 66 MHz in any state-of-the art ASIC technology and at 33 MHz on most FPGAs.
The design provides a simple, timing friendly backend interface that enables easy integration of the core to FIFOs, DMA controllers and other application specific backend logic.
The core provides numerous configuration options to include/exclude features to optimize the PCI interface for a particular implementation.