HDLC Controller

GDA's HDLC Controller is a single-channel HDLC controller core. The device contains a full-duplex transceiver with independent transmit and receive sections for bit-level HDLC protocol operations.

The core is designed for easy integration into wide range of applications implemented on most ASIC and FPGA technologies. The interface of this core can be adapted for a wide range of FIFO controllers. To be filled

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* -Generally sold with GDA services only

Features
Flag insertion and detection Abort generation and detection. Zero bit stuffing and deletion 16-bit CRC-CCITT generation and checking. CRC can be separately enabled and disabled for transmit.	Automatic insertion of 1 to 255 IDLE Characters between frames. Enable and data valid signals for flow control. Operates up to 155.52Mbit/s (STS-3) data rates.. Full-duplex operation.

Features

Flag insertion and detection

Abort generation and detection.

  Zero bit stuffing and deletion

  16-bit CRC-CCITT generation and checking.
  CRC can be separately enabled and disabled
    for transmit.

  Automatic insertion of 1 to 255 IDLE Characters
    between frames.

  Enable and data valid signals for flow control.
  Operates up to 155.52Mbit/s (STS-3) data rates..

  Full-duplex operation.