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RapidIO Serial and Parallel (GRIO)

The RapidIO Interconnect Architecture, designed to be compatible with the most popular integrated communications processors, host processors, and networking digital signal processors, is a high-performance, packet-switched, interconnect technology. It addresses the high-performance embedded industry's need for reliability, increased bandwidth, and faster bus speeds in an intra-system interconnect. The RapidIO interconnect allows chip-to-chip and board-to-board communications at performance levels scaling to ten Gigabits per second and beyond.

GDA's RapidIO controller core (GRIO) is designed to meet the growing needs of the industry. The core's simple, configurable and layered architecture is independent of applications, PHY designs, implementation tools and, most importantly, the target technology. The hardware and software configurable features make the core suitable for use in multiple applications. The design targets embedded systems, telecommunication, networking and any application where high speed, low latency response, low pin counts, reliability and scalability are necessary.


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* - Rambus IP; Sold under GDA’s Re-seller agreement with Rambus, Inc.



Features

  Compliant with RapidIO specification, Revision 1.3
 Supports both Serial and Parallel interfaces

  Supports 1x and 4x serial interfaces at 1.25/2.5/3.125Gbps

  Supports 8 and 16 bit parallel interfaces at 250/375/500 MHz

  Implements physical, transport and logical layer functions
  Supports both input/output and message passing protocols

  Implements receiver controlled flow control
  Supports all transaction flows and priorities

  Support for up to 256 bytes data payload

  Supports 34 bit addressing
  Implements a flexible buffer management scheme

  Performs link initialization, training, error detection
    and recovery
  Performs auto detection of interface widths
    and modes
  Targets FPGA, Structured ASIC and Standard
    Cell technologies
  Supports Multi-cast event control symbols

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