HyperTransport
technology is a highspeed, low-latency, point-to-point
link for interconnecting integrated circuits
(ICs) on a board. It is a packet-based link
implemented on two independent unidirectional
sets of wires. HyperTransport Host is the root
of the HyperTransport
fabric.
GDA's HyperTransport Host core is designed for
reuse and its flexible backend interface makes
it easy to be integrated into wide range of
applications. The core provides highly scalable
bandwidth through programmable link widths and
frequencies.
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Features |
- Compliant with HyperTransport
I/O Link
Specification, Ver. 1.03
- Can be hardware configured
for 16-bit or 8-bit link
Interface
- Supports software
programmable link widths of 16,8, 4
or 2 bits
- Supports 800, 600,
500, 400, or 200 MHz link
Frequency
- Maximum bandwidth is
6.4 Gb/sec
- Supports double-hosted
chain
- Supports link disconnect
protocol
- Supports peer-to-peer
transactions
- Supports reset generation
- Supports external
and internal loop backs
- Optional transaction
interface provides target and initiator
interfaces
- Optional packet interface
for network applications
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