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| HIGIG INTERCONNECT TECHNOLOGY |
APPLICATION – HiGig is the name for a Broadcom proprietary interconnect scheme. It refers primarily to the formatting of the packet for transmission between a particular family of Broadcom devices. The basic transmission method utilizes the Preamble field of an Ethernet packet and four bytes of interpacket gap to allow HiGig ports to connect to other HiGig ports.
HiGig protocol can be used in the switch devices to support features such as mirroring, link aggregation and quality of service across multiple devices in the system. This information is communicated via a module header that is prep ended to the beginning of each packet.
The physical signaling across the interface is via a 10Gbps attachment unit interface(XAUI) that complies with clause 47 of IEEE 802.3ae standard.
FEATURE SET OF HiGig Soft IP CORE – GDA Technologies Inc offering of the HiGig core is 10G Ethernet MAC core, which implements HiGig protocol.
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Main Featues
- 10 Gigabit Ethernet Media Access Controller compliant to IEEE 802.3ae
- Full duplex flow control compliant to IEEE 802.3x
- XGMII/XAUI interface on line side - compliant to IEEE 802.3ae
- 64-bit wide, Xilinx local link interface on system side
- Configurable depth for Rx and Tx FIFOs
- Store-and-forward and cut-through modes of operation
- Jumbo and short frame support
- Stat counters for RMON, SNMP, 802.3ae
- Maskable interrupts for major hardware events
System Interface
- 64-bit wide, Xilinx local link interface on system side
- Dedicated signals for per packet control and status information
- Auto and Software clear modes for Interrupt status bits
Optional
PHY Interface and Management
- XGMII / XAUI on PHY side
- Optional MDIO interface for PHY management
- Support for indirect addressing
- Programmable MDIO preamble suppression
- Supports management of multiple PHYs
Other Interfaces
- 32-bit PVCI for network management interface
- Well defined interface for the statistics block Optional
- Data FIFO, Hash Table memory and Pattern Match filter memory interfaces
Transmit
- HiGig header insertion - The complete HiGig header precedes the ethernet frame on the 64-bit local link interface. The HiGig header is provided by the user and it will not be implemented in the HiGig mac register space.
- FCS insertion. FCS will be calculated for the entire frame, including the higig header and appended.
- Programmable padding of under-sized frames
- Programmable minimum average inter packet gap (IPG)
- Link fault generation
Optional
Receive
- HiGig header extraction - The complete HiGig header precedes the ethernet frame on the 64-bit local link interface.
- FCS checking, stripping
- Valid length field checking
- Status logging and forwarding on per frame basis
- Capable of receiving continuous packets with 1 clock IPG
- Link fault detection and signaling
Optional
- Timestamp tagging of Receive frames (32-bit, external clock, external reset)
- Flexible address filtering options: unicast, multicast, broadcast and promiscuous
- Programmable option for error packet discard
Flow Control
- Full duplex flow control compliant to IEEE 802.3x
- Auto enable/disable of Tx block on PAUSE frame reception
- Programmable auto generation of PAUSE frames based on Rx FIFO watermarks
- Programmable PAUSE time for the MAC generated flow control frames.
- Optional supports for custom/in-band flow control
Filtering Options
- Promiscuous mode
- Broadcast storm control
Optional
- Configurable number of exact match UC/MC source/destination addresses
- Hash based filtering on MC address - configurable table size
- Wire-speed packet filtering based on programmable, 128-byte patterns
FIFO
- Configurable depth for Rx and Tx FIFOs
- Programmable threshold for cut-through mode of operation
- Programmable thresholds for PAUSE frame generation
- Programmable bit for FIFO flush
Optional
- Software access to Tx and Rx FIFOs
- Software access to FIFO pointers
Statistics Counters
- Separate design hierarchy for the statistics counters
- PVCI for network management interface
- Well defined vector interface with the Rx and Tx blocks
- Supports RMON, Ethernet, SNMP IG and SNMP Ethernet like group specifications
- Maskable interrupt on half or full roll overs
- Counters of configurable width (32 or 48)
Optional
- Optional reset-on-read
- Counter Freeze option
Hardware configurable Features
- Receive and Transmit FIFO depths
- Per frame status width
- Frame Time stamping
- Frame count at the receive local link interface
- Inclusion of Stat counter block
- Management interface width: 32
- Size of the MC hash tables
Software programmable Features
- Number of exact MAC addresses for receive packet filtering
- Inclusion of Station manager
- XGMII interface configured as SDR (i.e. 64bit @ 156.25) or DDR (i.e. 32bit @ 156.25 Both Edges with technology dependant DDR modules)
- Mode of data transfer: Cut-through or Store-and-forward
- Cut through mode thresholds
- Inter packet gap (IPG) for traffic shaping
- CRC strip options for receive packet
- Jumbo frame size
- Auto-pad, Auto depad enables and padding character
- Auto PAUSE and Auto zero PAUSE enables and thresholds
- Source address insertion enable
- Interrupt clear modes
- Pass on Errors
- Time stamp counter enable and start value
- Link fault generation enable
- Packet filtering options: MAC addresses, Hash entries, patterns etc.
- Packet Accept/Reject controls
- Pattern Match length
- Broadcast storm control enable and thresholds
- Flow control frame filter enable on DA unicast/Multicast
- Unicast and Multicast promiscuous enable
- Software resets for transmit and receive sections
- FIFO flush controls
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| * - Rambus IP; Sold under GDA’s Re-seller agreement with Rambus, Inc. |
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