Gen1 PCI Express Switch Port Controller

GDA's Gen1 PCI Express Switch controller is a highly flexible and configurable design targeted for switch implementations in desktop, server, mobile, networking and telecom applications. The controller architecture is carefully tailored to optimize link utilization, latency, reliability, power consumption, and silicon footprint.

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GPEX-SW is part of GDA's PCIExpress (GPEX) family of IP solutions, which includes End Point (GPEX-EP), Root Complex (GPEX-RC), Hybrid (GPEX-HY), Switch port Controller (GPEX-SW), Switch (GPEX-SWITCH) and Advanced Switching (GPEX-AS) designs. GPEX-SW comes in 2 flavors, Upstream Switch port and Downstream Switch Port. These flavors allow a Transparent PCIe Switch implementation with implementation specific port and Data path arbitration schemes.

The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. GDA solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible backend interface makes it easy to be integrated into wide range of applications.

* - Rambus IP; Sold under GDA’s Re-seller agreement with Rambus, Inc.

Features
Compliant to PCI Express base specificationversion 1.1 (2.5 Gbps) for Gen1 requirements Compliant with PCI-to-PCI Bridge Architecture Specification Revision 1.2 Implements transaction, data link and physical layers Internal data path width: 64 or 128 bits Supports Type1 configuration space Allows access to port configuration space from line and GPI Supports Type0/1 configuration conversions	Debug and Test Features Supports multiple lanes: x1, x2, x4, x8 or x16 Architected for high link utilization and low latency Efficient receive and transmit-retry buffering scheme Completely handles PCI-Express ordering rules Implements flow control logic for both directions Supports PIPE based PHY architecture Flexible lane ordering and support for lane reversal Optional packet buffer and scheduler modules Supports configurable number of downstream ports Supports parallel address decoding Handling of UR for both upstream and downstream traffic

Features

Compliant to PCI Express base specificationversion 1.1 (2.5 Gbps) for Gen1 requirements

Compliant with PCI-to-PCI Bridge Architecture Specification Revision 1.2

    Implements transaction, data link and physical layers
   Internal data path width: 64 or 128 bits

   Supports Type1 configuration space
   Allows access to port configuration space from line and GPI

Supports Type0/1 configuration conversions

Debug and Test Features

  Supports multiple lanes: x1, x2, x4, x8 or x16

   Architected for high link utilization and low latency

  Efficient receive and transmit-retry buffering scheme

  Completely handles PCI-Express ordering rules

Implements flow control logic for both directions

  Supports PIPE based PHY architecture

  Flexible lane ordering and support for lane reversal

  Optional packet buffer and scheduler modules

  Supports configurable number of downstream ports

  Supports parallel address decoding

  Handling of UR for both upstream and downstream traffic