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Gen1 PCI Express - AXI Bridge

Product Brief

Applications

* PC’s workstations and servers
* Storage
* Networking and communications
* Switches and routers

Benefits

* Verified with leading AXI VIP
* Superior architecture-high performance, low latency and low gate count
* Feature rich, highly flexible, scalable, configurable and timing friendly design
* Ease of integration


Superior Architecture

The GDA PCI Express*-AMBA AXI Bridge (PCIe-AXI Bridge) is a highly flexible and configurable IP with a PCI Express interface on one side and an AMBA AXI interface on the system side. The Bridge has been architectured to interface with a PCI Express controller used as an end-point or root-complex type devices. The PCIe-AXI BRIDGE uses high speed multi-channel DMA controllers to match the bandwidth requirements of the PCIe Gen2 solution.

The GDA PCI Express-AXI Bridge is a simple, configurable and layered architecture, independent of applications, implementation tools or target technology. The controller architecture is carefully tailored to optimize latency, power consumption, and silicon footprint, making it ideal for cost and performance sensitive applications. The PCIe-AXI BRIDGE solution provides highly scalable bandwidth through a configurable data path width and clock frequency,

Most Thoroughly Verified and Interoperable Design

The GDA PCIe-AXI BRIDGE is an exhaustively verified solution tested with high coverage design specific as well as random tests. The IP is verified with leading AXI verification IP and the verification environment can be configured to run with all the major simulators. The reusable block level verification environment and the formal verification methodology enhance the quality of verification process and add more confidence to the design verification

The GDA PCI Express-AXI Bridge solution leverages years of experience in creating reusable IP solutions for Ethernet, RapidIO and PCI Express technologies. The expertise in creating those system validated solutions with RTL, synthesis, simulation, board and software elements ensures delivery of lower risk, compliant and interoperable solution.

Ease of Integration


The GDA PCI Express- AXI Bridge design is fully synchronous and adheres to standard synthesis, test insertion and physical design practices. The solution allows licensees to easily migrate among COT, FPGA, Gate array, structured ASIC and Standard cell technologies. The design with its flexible user logic interface can be easily integrated into a wide range of applications.

Superior Support

The PCIe-AXI BRIDGE solution comes with a superior support model that offers round the clock telephone, email, web based support and free code updates during the support period. Support documents including a data sheet, design guide, verification guide, synthesis guide and application notes are also offered. To build a full-system solution the GDA partner eco-system provides access to additional components such as verification IP, PHYs and related design services.

Design Configurability

The design offers enormous hardware and software configurable options allowing the user to choose the optimal solution to meet his requirement. The configuration options include

* PIO, DMA or mixed mode of operation
* Up to 8 Read and Write DMA supported
* Up to 8 PCI Express capable AXI Slave PIO devices supported
* Up to 8 AXI capable PCI Express PIO devices supported
* Maximum DMA transfer size of 1 MB
* Register based or Chain Descriptor based DMA types
* Priority level transaction initiations by different DMA/PIO devices
* Programmable address mapping for PIO transfers
* Programmable PCI Express tags reserved for each DMA/PIO device
* PCI Express or AMBA hosted DMA accesses
* AXI or APB register space accesses
* System clock frequency
* Synchronous/Asynchronous reset

Deliverables

The deliverables include

* Verilog RTL
* Behavioral test bench and test cases
* PCI Express and Application BFM
* ASIC Synthesis environment
* Documentation

*PCI Express is a registered trademark of the PCI-SIG. GDA IP; Sold under GDA’s Re-seller agreement with Rambus, Inc.



Features

  Compliant with PCI Express Base 1.1 or 2.0
    Specifications

   AMBA AXI protocol 1.0 compliant

 AXI PIO operation with configurable number of AXI     Slaves supported

   Multi-channel DMA transfers supported
  Register based and descriptor based modes of      DMA supported

   Read and write DMAs supported
  Interrupt generation to both AXI and PCI Express         supported

   Vendor defined messages supported
   Software configurable address mapping between
     PCI Express and AXI systems

   Exhaustive Control, Status and Debug registers
   CSR registers optional access through APB

PCI Express Features

  Maximum link width: x16 link
  Max payload size of 4096B

  Up to 8 Virtual Channels supported
  Up to 8 functions supported
  Data path width: 32, 64 and 128-bits
  Efficient Receive VC buffer implementation

  Configurable Receive VC buffer size

  PCI Express ordering rules implemented
  INTx, MSI and MSI-X interrupt mechanisms

Debug and Test Features
The solution provides comprehensive debug and test features such as
  Implementation specific registers for debugging
  Comprehensive error reporting
  Mailbox registers for higher layer information exchange
  Performance monitors
  Debug mode for descriptor based DMA

  Interrupt generation for debug mode events

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