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RapidIO- AXI Bridge

Applications

* PC’s workstations and servers
* Wireless Baseband and CPE
* Networking and communications
* Switches

Benefits

* Verified with RapidIO Trade Association VIP
* Superior architecture-high performance, low latency and low gate count
* Feature rich, highly flexible, scalable, configurable and timing friendly design
* Ease of integration


Superior Architecture

The GDA RapidIO-AMBA AXI Bridge (RIO-AXI Bridge) is a highly flexible and configurable IP with a RIO interface on one side and an AXI interface on the system side. The Bridge has been architectured to interface with a RapidIO controller used as a Host or device. The RIO-AXI BRIDGE uses high speed multi-channel DMA and Message controllers to match the bandwidth requirements of the RIO solution.


The GDA RIO-AXI Bridge is a simple, configurable and layered architecture, independent of applications, implementation tools or target technology. The controller architecture is carefully tailored to optimize latency, power consumption, and silicon footprint, making it ideal for cost and performance sensitive applications. The RIO-AXI BRIDGE solution provides highly scalable bandwidth through a configurable data path width and clock frequency,

Most Thoroughly Verified and Interoperable Design

The GDA RIO-AXI BRIDGE is an exhaustively verified solution tested with high coverage design specific as well as random tests. The IP is verified with RapidIO Trade association verification IP and the verification environment can be configured to run with all the major simulators. The reusable block level verification environment and the formal verification methodology enhance the quality of verification process and add more confidence to the design verification

The GDA RIO-AXI Bridge solution leverages years of experience in creating reusable IP solutions for Ethernet, Hypertransport and PCI Express technologies. The expertise in creating those system validated solutions with RTL, synthesis, simulation, board and software elements ensures delivery of lower risk, compliant and interoperable solution. simulation, board and software elements ensures delivery of lower risk, compliant and interoperable solution

Ease of Integration

The GDA RIO- AXI Bridge design is fully synchronous and adheres to standard synthesis, test insertion and physical design practices. The solution allows licensees to easily migrate among COT, FPGA, Gate array, structured ASIC and Standard cell technologies

Superior Support

The RIO-AXI BRIDGE solution comes with a superior support model that offers round the clock telephone, email, web based support and free code updates during the support period. Support documents including a data sheet, design guide, verification guide, synthesis guide and application notes are also offered. To build a full-system solution the GDA partner eco-system provides access to additional components such as verification IP, PHYs and related design services.

Design Configurability

The design offers enormous hardware and software configurable options allowing the user to choose the optimal solution to meet his requirement. The configuration options include

* PIO, DMA or mixed mode of operation
* PIO, DMA, Message or mixed mode of operation
* Up to 8 Read and Write DMA Channels
* Up to 8 RapidIO capable AXI Slave PIO devices
* Up to 8 AXI capable RapidIO devices
* Maximum DMA transfer size of 1 MB
* Register based or Chain Descriptor based DMA types
* Priority level transaction initiations by different DMA/PIO devices
* Programmable address mapping for PIO transfers
* RapidIO or AMBA hosted DMA accesses
* AXI or APB register space accesses
* System clock frequency
* Synchronous/Asynchronous reset

Deliverables

* Verilog RTL
* Behavioral test bench and test cases
* AMBA AXI, and RapidIO BFM
* ASIC Synthesis environment
* Documentation


GRIO IP, part of RapidIO-AXI Bridge is sold under GDA’s Re-seller agreement with Rambus, Inc.



Features

  RapidIO to AMBA AXI Bridge complaint to RapidIO
   1.3 specification

   Compliant to AMBA AXI protocol v1.0

   Supports 32-bit or 38-bit addressing

   AXI PIO operation with configurable number
    of AXI Slaves
   RapidIO PIO operation with configurable number
    of AXI Masters

   Multi-channel Read and Write DMA
   Register based and descriptor based
    modes of DMA

   Interrupt generation to both AXI and RapidIO
   Inbound and Outbound Doorbell

  Logical Flow control
  Bypass Mode

  Software configurable address mapping between
    RapidIO and AXI systems
  Exhaustive Control, Status and Debug registers

  CSR registers optional access through APB
  Inbound and Outbound Mailbox Support
  Configurable number of Outbound Letters

  Configurable number of Inbound Letters
  Supports 64 and 128 bit datapath

                 RapidIO Features

  Compliant to RapidIO Specifications revision 1.3
  Implements Logical, Transport and Physical layers
  Supports 1x and 4x serial interface and 8 and 16
   bits parallel interface

  Supports RapidIO Input output logical
   specification revision 1.3
  Supports common transport specification revision 1.3
  Support for register and register bit extensions as
   described in Part VIII: Error Management Extensions
   Specification revision 1.3

  Supports up to 256 Bytes data payload
  Supports hardware error recovery
  Supports small and large size transport ID)

  Supports all transaction flows and all priorities
  Supports request class transaction: NREAD
  Supports write class transaction: NWRITE, NWRITE_R

  Supports Streaming write class transaction: SWRITE
  Supports Maintenance transactions, including IB Port-Write
  Supports Message passing: Data and Doorbell Message

                  Debug and Test Features

The solution provides comprehensive debug and test
features such as
  Implementation specific registers for debugging
  Comprehensive error reporting
  Mailbox registers for higher layer information exchange
  Performance monitors
  Debug mode for descriptor based DMA