IBM PowerPC 460S Core
Supporting Single and Multi-Processor SoC Designs

New applications like Online Gaming, Web 2.0 and Mobile TV are increasing the data usage significantly. These applications have live streaming of data that promotes 3rd Generation Partnership Project (3GPP) to work on the Long-Term Evolution (LTE). LTE is the next generation of GSM/EDGE and High Speed Packet Access (HSPA) network technologies. GDA plans to significantly increase throughput of these applications by enabling PowerPC based LTE stacks and LTE base stations (eNode B). Complete hardware and software components based on PowerPC Architecture will deliver superior Quality of Service (QoS) for WiMAX/LTE systems required by applications like IPTV and VOIP. GDA plans to harden the PowerPC 460S for proven, reliable integration into SoCs. Hardened 460S cores will be optimized for performance, power, and size for specific technologies and applications.

The IBM PowerPC® 460S core is a 32-bit high performance, low-power embedded processor core that is fully compliant with the flexible and scalable IBM Power Architecture™, Power ISA™ 2.03. As a synthesizable core, the PowerPC 460S provides the flexibility of fabrication in multiple foundries. The PowerPC 460S core allows the system-on-chip (SoC) designer to select the cache size and processor local bus (PLB) version necessary to optimize single processor and cache coherent multi-processor SoC designs. The PowerPC 460S design flexibility and scalability will meet the performance and power demands of today’s communications, consumer electronics and storage embedded applications.

The PowerPC 460S contains a dual-issue, superscalar, pipelined processing unit. The core includes memory management, cache control, timers and debug facilities. Interfaces for custom co-processors and floating point functions are provided, along with separate instruction and data cache array interfaces, which can be configured to various sizes

The PowerPC 460 core can be integrated with peripheral and application-specific macro cores using the IBM CoreConnect™ bus architecture to develop custom SoC solutions. GDA also offers interface IP cores such as DDR 2/3 memory controllers, DMA and interrupt controllers, PCI controllers (PCI, PCI-X, PCIe), Serial RIO, 1/10GE, HT, Display Port, HDMI, and Interlaken controllers. GDA offers through its PES group custom services to design complex SoC’s.

A comprehensive portfolio of PowerPC family support tools is available through the extensive IBM Business Partners network. Offerings include peripheral IP, operating systems, compilers, debuggers, simulators and emulators and design services. The PowerPC 460 core is designed to work with industry-standard EDA tools, including SystemC models.

PowerPC 460S core features:

High performance, dual issue, superscalar      32-bit RISC CPU    High bandwidth PLB interface    Power ISA 2.03 compliant    32 x 32-bit general purpose registers (GPR)    Seven-stage pipeline    Dynamic branch prediction    Static design with extensive clock and      power management support    24 DSP instructions L1 cache    Configurable 16KB or 32KB I-side and D-side      cache with parity    Write-back, write-through, non blocking    Cache line locking (I and D)    Parity error detection and recovery

Memory Management Unit    64-entry, fully-associative unified translation      look-aside buffer (TLB) with parity   Separate I and D side micro-TLBs   Flexible TLB management   Optimized for embedded applications   Variable page sizes (1KB – 1GB)    CoreConnect Bus Interface   Supports three Master ports on PLB   Takes advantage of PLB request pipelining   64-bit address width with extended      address pipelining   Hidden bus request/grant protocol      reduces arbitration latency   Supports multiple CPU to PLB frequency      ratios and bus snooping     Timers   64-bit time-base   32-bit decrementer   Fixed interval timer   Watchdog timer