The AHB 3.0 IP Core provides all the components necessary to build an AHB system of any configuration using a mixture of AHB standard and AHB Lite Master and Slaves. The block diagram shows an example system that uses all these components.
Standard AHB Master, Standard AHB Slave and AHB Arbiter are fully compliant to AHB 2.0. Lite AHB Master and Lite AHB Slave are fully compliant to AHB-Lite 1.0. The interconnect Matrix support up to 16 Layers |
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| GDA Technologies Inc. is a leading Electronic Design Services (EDS) and Silicon Intellectual Property (SIP) solution provider for the Embedded, Networking, and Consumer Electronics Markets. GDA is focused on designing IC and board level products from concept to implementation. GDA has successfully developed products in areas of high-speed communications, Digital Video, Internet Appliances, and Mobile Solutions. |
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IP Status
- RTL coding done
- Functional Verification done
- FPGA Validation done
Product Package
- Highly Configurable RTL code using the VPP option
- Detailed Design/Verification document
- Verification environment
- Test cases
- Coverage Reports
- Synthesis environment/Scripts
Documentation
- User Guide
- Synthesis Guide
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Components delivered: -
- AHB 2.0 Master
- AHB 2.0 Slave
- AHB Lite Master
- AHB Lite Slave
- AHB Decoder and Muxes
- AHB Arbiter
- Interconnect Matrix
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Language :Verilog HDL
Synthesis :RTL Compiler
Simulation :NC-Verilog
Technology :Technology Independent RTL |
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Feature of the AHB 3.0 IP Core |
| Video Inputs |
- Configurable Address width
- Configurable number of masters (1 to 16)
- Configurable number of slaves (1 to 16)
- Selectable Arbitration types (Round robin/ fixed)
- Interconnect Matrix can support up to 16 Master ports and 16 Slave ports
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